PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

Industrial-grade UVM 1.2 environment for a full-duplex UART controller. Features Constrained Random Verification (CRV), weighted stress-testing, and multi-baudrate regression (9600–115200) using Questa Sim.