Hardware Design & Verification Engineer | RISC-V Architecture | UVM & SystemVerilog

I specialize in the functional verification of complex SoC interconnects and the design of high-performance RISC-V accelerators. My work focuses on bridging the gap between architectural specifications and silicon-ready RTL through industrial-grade verification methodologies.

• Verification: UVM 1.2, SystemVerilog, CRV, Coverage-Driven Verification, Scoreboarding.
• Design & Implementation: RTL (Verilog/SV), MMMC Synthesis, PPA Optimization, Gate-Level Simulation (GLS).
• Protocols & Arch: RISC-V (RV32IMF), AMBA AXI4, CHI, Wishbone, Superscalar Pipelines.
• EDA Tools: Cadence Genus & Xrun, Xilinx Vivado, Siemens Questa, Synopsys DC.

A modular ecosystem for verifying AXI4 Master and Slave IPs. Features unaligned access testing, byte-level strobe management, and handshake saturation logic.

FPGA implementation of the "Hornet" RV32IMF processor. Optimized memory drivers and custom RTL to enable real-time AI inference workloads on hardware.

A deep-dive into physical implementation trade-offs between FF and Latch-based 2W4R Register Files.

• Flow: Cadence Genus MMMC synthesis (4 corners), SDF back-annotation, and functional GLS.
• Insight: Evaluated area efficiency vs. timing bottlenecks in clock-gating logic.
• Note: Repository private to comply with PDK/Vendor NDAs. Reports available upon request.

Industrial-grade UVM environment for full-duplex UART controllers, featuring constrained-random stress testing and multi-baudrate regression.